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preliminary 18-mbit (512k x 36/1m x 18) flow-through sram with nobl? architecture cy7c1371d cy7c1373d cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05556 rev. *a revised november 3, 2004 features ? no bus latency ? (nobl ? ) architecture eliminates dead cycles between write and read cycles ? can support up to 133-mhz bus operations with zero wait states ? data is transferred on every clock ? pin-compatible and functionally equivalent to zbt? devices ? internally self-time d output buffer cont rol to eliminate the need to use oe ? registered inputs for flow-through operation ? byte write capability ? 3.3v/2.5v i/o power supply ? fast clock-to-output times ? 6.5 ns (for 133-mhz device) ? 8.5 ns (for 100-mhz device) ? clock enable (cen ) pin to enable clock and suspend operation ? synchronous self-timed writes ? asynchronous output enable ? offered in jedec-standard lead-free 100 tqfp, 119-ball bga and 165-ball fbga packages ? three chip enables for simple depth expansion ? automatic power-down feature available using zz mode or ce deselect ? jtag boundary scan for bga and fbga packages ? burst capability?linear or interleaved burst order ? low standby power functional description [1] the cy7c1371d/cy7c1373d is a 3.3v, 512k x 36/1 mbit x 18 synchronous flow-through burst sram designed specifi- cally to support unlimited true back-to-back read/write opera- tions without the insertion of wait states. the cy7c1371d/ cy7c1373d is equipped with the advanced no bus latency (nobl) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the throughput of data through the sram, especially in systems that r equire frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock rise is 6.5 ns (133-mhz device). write operations are controlled by the two or four byte write select (bw x ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. in order to avoid bus contention, the output driver s are synchronously tri-stated during the data portion of a write sequence. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 210 175 ma maximum cmos standby current 70 70 ma note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 2 of 30 1 2 c mode bw a bw b we ce1 ce2 ce3 oe read ? logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write ? registry and ? data ? coherency control ? logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control logic block diagram ? cy7c1371d (512k x 36) c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control logic block diagram ? cy7c1373d (1 mbit x 18)
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 3 of 30 pin configurations 100-lead tqfp a a a a a1 a0 nc / 288m nc / 144m v ss v dd nc / 36m a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc / 72m cy7c1371d byte a byte b byte d byte c a
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 4 of 30 pin configurations (continued) 100-lead tqfp a a a a a1 a0 nc / 288m nc / 144m v ss v dd nc / 36m a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc / 72m cy7c1373d byte a byte b a
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 5 of 30 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqp c dq c dq d dq c dq d aa aav ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms nc / 36m nc / 72m nc v ddq v ddq v ddq aaa a ce 3 a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adv/ld nc ce 1 oe a we v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc cen bw d zz 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc nc nc dq b dq b dq b dq b aa aav ddq ce 2 a nc v ddq nc v ddq v ddq v ddq nc nc nc nc / 72m v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms a a nc v ddq v ddq v ddq a nc / 36m a a ce 3 a a a a a a a0 a1 dq a dq b nc nc dq a nc dq a dq a nc nc dq a nc dq a nc dq a nc dq a v dd nc dq b nc v dd dq b nc dq b nc adv/ld nc ce 1 oe a we v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqp b dqp a nc bw b nc v dd nc bw a nc cen nc zz cy7c1373d (1 mbit x 18) cy7c1371d (512k x 36) 119-ball bga (3 chip enables with jtag) a a
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 6 of 30 pin configurations (continued) 165-ball fbga (3 chip enable with jtag) cy7c1371d (512k x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc / 36m nc / 72m v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 nc a a adv/ld nc oe a nc / 144m v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss nc cy7c1373d (1 mbit x 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc nc nc dqp b nc dq b ce 1 nc ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc nc / 36m nc / 72m v ddq nc bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 nc a a adv/ld a oe a nc / 144m v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a0 a v ss nc a a
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 7 of 30 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. a [1:0] are fed to the two-bit burst counter. bw a , bw b bw c , bw d input- synchronous byte write inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input . used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/desel ect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, asynchronous input, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the firs t clock when emerging from a deselected state, when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recog- nized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preser ved. during normal operation, this pin can be connected to v ss or left floating. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycl e. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp [a:d] are placed in a tri-state condition.the outputs are automatically tri-stated during the data portion of a write sequence, during the firs t clock when emerging from a deselected state, and when the device is desel ected, regardless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . mode input strap pin mode input. selects the burst order of the device. when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilized, this pin should be left unconnected. this pin is not available on tqfp packages.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 8 of 30 functional overview the cy7c1371d/cy7c1373d is a synchronous flow-through burst sram designed specifically to eliminate wait states during write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recog- nized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw x can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and 4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another oper ation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. burst read accesses the cy7c1371d/cy7c1373d has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequ ence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a 0 and a 1 in the burst sequence, and will wrap around when incremented suffi- ciently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tri-stated regar dless of the state of the oe input signal. this allows the external logic to present the data on dqs and dqp x . on the next clock rise the data presented to dqs and dqp x (or a subset for byte write o perations, see truth table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the wr ite operation is controlled by bw x signals. the cy7c1371d/cy7c1373d provides byte write capability that is described in the truth table. asserting the write enable input (we ) with the selected byte write select input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self -timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1371d/cy7c1373d is a common i/o device, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp x inputs. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising ed ge of tck. if the jtag feature is not being utilized, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising ed ge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to the jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the di e. 36 mbit, 72 mbit, 144 mbit and 288 mbit are address expansion pins and ar e not internally connected to the die. pin definitions (continued) name i/o description
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 9 of 30 doing so will tri-state the output drivers. as a safety precaution, dqs and dqp x are automatically tri-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1371d/cy7c1373d has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operat ions without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write access section above. when adv/ld is driven high on the subse- quent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw x inputs must be driven in each cycle of the burst write, in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 80 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns truth table [ 2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tri-state deselect cycle none x x h l l x x x l l->h tri-state deselect cycle none x l x l l x x x l l->h tri-state continue deselect cycle none x x x l h x x x l l->h tri-state read cycle (begin burst) external l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tri-state dummy read (continue burst) next x x x l h x x h l l->h tri-state notes: 2. x = ?don't care.? h = logic high, l = logic low. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 3. write is defined by bw x , and we . see truth table for read/write. 4. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 5. the dqs and dqp x pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. cen = h, inserts wait states. 7. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 8. oe is asynchronous and is not sampled with the clock rise. it is masked internally duri ng write cycles. during a read cycle dqs a nd dqp x = tri-state when oe is inactive or when the device is deselected, and dqs and dqp x = data when oe is active.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 10 of 30 ieee 1149.1 serial boundary scan (jtag) the cy7c1371d/cy7c1373d incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this part operates in accordance with ieee standard 1149.1-1900, but doesn?t have the set of functions required for full 1149.1 compliance. these functions fr om the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tapoperates using jedec-standard 3.3v or 2.5v i/o logic levels. the cy7c1371d/cy7c1373d contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. note: 9. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write will be done based on which byte write is active. write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tri-state write abort (continue burst) next x x x l h x h x l l->h tri-state ignore clock edge (stall) current x x x l x x x x h l->h ? sleep mode none x x x h x x x x x x tri-state truth table (continued) [ 2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq partial truth table for read/write [2, 3, 9] function (cy7c1371d) we bw a bw b bw c bw d read hxxxx write no bytes written lhhhh write byte a ? (dq a and dqp a ) l lhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d ) lhhhl write all bytes lllll partial truth table for read/write [2, 3,9] function (cy7c1373d) we bw a bw b read h x x write - no bytes written l h h write byte a ? (dq a and dqp a )lhh write byte b ? (dq b and dqp b )lhh write all bytes l l l
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 11 of 30 tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any register. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machi ne. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the boa rd-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram i/o ring when the tap co ntroller is in the capture-dr test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 12 of 30 state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it per forms a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the ta p may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 13 of 30 tap timing tap ac switching characteristics over the operating range [10, 11] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 25 ns t tl tck clock low time 25 ns output times t tdov tck clock low to tdo valid 5 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 10. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns. t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 14 of 30 3.3v tap ac test conditions input pulse levels ............................................... .v ss to 3.3v input rise and fall times ......... .......................................... 1 ns input timing referenc e levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply vo ltage...............................1.5v 3.3v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels................................................. v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels... ..................................... .1.25v output reference levels .......... ...................................... 1.25v test load termination supply voltage ............................ 1.25v 2.5v tap ac output load equivalent note: 12. all voltages referenced to v ss (gnd). t do 1.5v 20p f z = 50 ? o 50 ? t do 1.25v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < ta < +70c; v dd = 3.3v 0.165v unless otherwise noted) [12] parameter description description conditions min. max. unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3v 2.4 v i oh = ?1.0 ma v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.5 0.7 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 15 of 30 identification register definitions instruction field cy7c1371d (512kx36) cy7c1373d (1 mbitx18) description revision number (31:29) 000 000 describes the version number device depth (28:24) 01011 01011 reserved for internal use device width (23:18) 001001 001001 defines memory type and architecture cypress device id (17:12) 100101 010101 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 allows unique identification of sram vendor id register presence indicator (0) 1 1 ind icates the presence of an id register scan register sizes register name bit size (x36) bit size (x18) instruction 3 3 bypass 1 1 id 32 32 boundary scan order (119-ball bga package) 85 85 boundary scan order (165-ball fbga package) 89 89 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. pl aces the boundary scan regi ster between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 16 of 30 119-ball bga boundary scan [13, 14] cy7c1371d (1 mbit x 36) cy7c1371d (1 mbit x 36) bit # ball id bit # ball id bit # ball id 1 h4 37 b6 73 n2 2t438d4 74p2 3t539b4 75r3 4 t640f4 76t1 5 r541m4 77r1 6l542a5 78t2 7r643k4 79l3 8 u644e4 80r2 9r745g4 81t3 10 t7 46 a4 82 l4 11 p6 47 g3 83 n4 12 n7 48 c3 84 p4 13 m6 49 b2 85 internal 14 l7 50 b3 15 k6 51 a3 16 p7 52 c2 17 n6 53 a2 18 l6 54 b1 19 k7 55 c1 20 j5 56 d2 21 h6 57 e1 22 g7 58 f2 23 f6 59 g1 24 e7 60 h2 25 d7 61 d1 26 h7 62 e2 27 g6 63 g2 28 e6 64 h1 29 d6 65 j3 30 c7 66 2k 31 b7 67 l1 32 c6 68 m2 33 a6 69 n1 34 c5 70 p1 35 b5 71 k1 36 g5 72 l2 notes: 13. balls which are nc (no connect) are pre-set low 14. bit# 85 is pre-set high
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 17 of 30 119-ball bga boundary scan order [13, 14] cy7c1373d (2m x 18) cy7c1373d (2m x 18) bit # ball id bit # ball id bit # ball id 1 h4 37 b6 73 n2 2t438d4 74p2 3t539b4 75r3 4 t640f4 76t1 5 r541m4 77r1 6l542a5 78t2 7r643k4 79l3 8 u644e4 80r2 9r745g4 81t3 10 t7 46 a4 82 l4 11 p6 47 g3 83 n4 12 n7 48 c3 84 p4 13 m6 49 b2 85 internal 14 l7 50 b3 15 k6 51 a3 16 p7 52 c2 17 n6 53 a2 18 l6 54 b1 19 k7 55 c1 20 j5 56 d2 21 h6 57 e1 22 g7 58 f2 23 f6 59 g1 24 e7 60 h2 25 d7 61 d1 26 h7 62 e2 27 g6 63 g2 28 e6 64 h1 29 d6 65 j3 30 c7 66 2k 31 b7 67 l1 32 c6 68 m2 33 a6 69 n1 34 c5 70 p1 35 b5 71 k1 36 g5 72 l2
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 18 of 30 165-ball fbga boundary scan order [13, 15] cy7c1371d (1 mbit x 36) cy7c1371d (1 mbit x 36) bit # ball id bit # ball id bit # ball id 1 n637a9 73k2 2n738b9 74l2 310n39c10 75m2 4 p11 40 a8 76 n1 5 p841b8 77n2 6 r842a7 78p1 7 r943b7 79r1 8 p944b6 80r2 9 p10 45 a6 81 p3 10 r10 46 b5 82 r3 11r1147a5 83p2 12 h11 48 a4 84 r4 13n1149b4 85p4 14 m11 50 b3 86 n5 15 l11 51 a3 87 p6 16 k11 52 a2 88 r6 17 j11 53 b2 89 internal 18 m10 54 c2 19 l10 55 b1 20 k10 56 a1 21 j10 57 c1 22 h9 58 d1 23 h10 59 e1 24 g11 60 f1 25 f11 61 g1 26 e11 62 d2 27 d11 63 e2 28 g10 64 f2 29 f10 65 g2 30 e10 66 h1 31 d10 67 h3 32 c11 68 j1 33 a11 69 k1 34 b11 70 l1 35 a10 71 m1 36 b10 72 j2 note: 15. bit# 89 is pre-set high.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 19 of 30 165-ball fbga boundary scan order [13, 15] cy7c1373d (2m x 18) cy7c1373d (2m x 18) bit # ball id bit # ball id bit # ball id 1 n637a9 73k2 2n738b9 74l2 310n39c10 75m2 4 p11 40 a8 76 n1 5p841b8 77n2 6 r842a7 78p1 7 r943b7 79r1 8p944b6 80r2 9 p10 45 a6 81 p3 10 r10 46 b5 82 r3 11r1147a5 83p2 12 h11 48 a4 84 r4 13n1149b4 85p4 14 m11 50 b3 86 n5 15 l11 51 a3 87 p6 16 k11 52 a2 88 r6 17 j11 53 b2 89 internal 18 m10 54 c2 19 l10 55 b1 20 k10 56 a1 21 j10 57 c1 22 h9 58 d1 23 h10 59 e1 24 g11 60 f1 25 f11 61 g1 26 e11 62 d2 27 d11 63 e2 28 g10 64 f2 29 f10 65 g2 30 e10 66 h1 31 d10 67 h3 32 c11 68 j1 33 a11 69 k1 34 b11 70 l1 35 a10 71 m1 36 b10 72 j2
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 20 of 30 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +4.6v dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [16, 17] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage v ddq = 3.3v 3.135 v dd v v ddq = 2.5v 2.375 2.625 v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage [16] v ddq = 3.3v 2.0 v dd + 0.3v v v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [16] v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load gnd v i v ddq ?5 5 a input current of mode input = v ss ?5 a input = v dd 30 a input current of zz input = v ss ?30 a input = v dd 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 210 ma 10-ns cycle, 100 mhz 175 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max , inputs switching 7.5-ns cycle, 133 mhz 140 ma 10-ns cycle, 100 mhz 120 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v dd ? 0.3v, f = 0, inputs static all speeds 70 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max , inputs switching 7.5-ns cycle, 133 mhz 130 ma 10-ns cycle, 100 mhz 110 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v dd ? 0.3v or v in 0.3v , f = 0, inputs static all speeds 80 ma notes: 16. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 17. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 21 of 30 note: 18. tested initially and after any design or proc ess change that may affect these parameters. thermal resistance [18] parameter descriptio n test conditions tqfp package bga package fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 31 45 46 c/w jc thermal resistance (junction to case) 673 c/w capacitance [18] parameter description test conditions tqfp package bga package fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v v ddq = 2.5v 589pf c clk clock input capacitance 5 8 9 pf c i/o input/output capacitance 5 8 9 pf ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 22 of 30 switching characteristics over the operating range [23, 24] parameter description 133 mhz 100 mhz unit min. max. min. max. t power [19] 11ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.1 2.5 ns t cl clock low 2.1 2.5 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold after clk rise 2.0 2.0 ns t clz clock to low-z [20, 21, 22] 2.0 2.0 ns t chz clock to high-z [20, 21, 22] 4.0 5.0 ns t oev oe low to output valid 3.2 3.8 ns t oelz oe low to output low-z [20, 21, 22] 00ns t oehz oe high to output high-z [20, 21, 22] 4.0 5.0 ns setup times t as address set-up befo re clk rise 1.5 1.5 ns t als adv/ld set-up before clk rise 1.5 1.5 ns t wes we , bw x set-up before clk rise 1.5 1.5 ns t cens cen set-up before clk rise 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t ces chip enable set-up before clk rise 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes: 19. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 20. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 21. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not impl y a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 22. this parameter is sampled and not 100% tested. 23. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 24. test conditions shown in (a) of ac test loads unless otherwise noted.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 23 of 30 switching waveforms read/write waveforms [25, 26, 27] notes: 25. for this waveform zz is tied low. 26. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 27. order of the burst sequence is determined by the status of th e mode (0 = linear, 1 = interleaved). burst operations are opti onal. 3 write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6)
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 24 of 30 nop, stall and deselect cycles [25, 26, 28] note: 28. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a writ e is not performed during this cycle. switching waveforms (continued) write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6)
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 25 of 30 4 zz mode timing [29, 30] notes: 29. device must be deselected when entering zz mode. see truth ta ble for all possible signal conditions to deselect the device. 30. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 26 of 30 ordering information speed (mhz) ordering code package name part and package type operating range 133 cy7c1371d-133axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1373d-133axc cy7c1371d-133axi cy7c1373d-133axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1371d-133bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag commercial cy7c1373d-133bgc cy7c1371d-133bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag industrial cy7c1373d-133bgi cy7c1371d-133bzc bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1373d-133bzc cy7c1371d-133bzi bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1373d-133bzi cy7c1371d-133bgxc bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag commercial cy7c1373d-133bgxc cy7c1371d-133bgxi bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag industrial cy7c1373d-133bgxi cy7c1371d-133bzxc bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm)3 chip enables and jtag commercial cy7c1373d-133bzxc cy7c1371d-133bzxi bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm)3 chip enables and jtag industrial cy7c1373d-133bzxi 100 cy7c1371d-100axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1373d-100axc CY7C1371D-100AXI a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1373d-100axi cy7c1371d-100bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag commercial cy7c1373d-100bgc cy7c1371d-100bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag industrial icy7c1373d-100bgi cy7c1371d-100bzc bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1373d-100bzc cy7c1371d-100bzi bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1373d-100bzi cy7c1371d-100bgxc bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag commercial cy7c1373d-100bgxc cy7c1371d-100bgxi bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag industrial icy7c1373d-100bgxi cy7c1371d-100bzxc bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag commercial cy7c1373d-100bzxc cy7c1371d-100bzxi bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag industrial cy7c1373d-100bzxi shaded areas contain advance information. plea se contact your local sales representative for availability of these parts. lead- free bg packages (ordering code: bgx) will be available in 2005.
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 27 of 30 package diagrams dimensions are in millimeters. 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r0.08min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 28 of 30 package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 29 of 30 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. nobl and no bus latency are trademarks of cypress semiconduct or corporation. i486 is a trad emark, and intel and pentium are registered trademarks of intel corporat ion. powerpc is a trademark of ibm co rporation. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85180-** 165 fbga 13 x 15 x 1.40 mm bb165d
preliminary cy7c1371d cy7c1373d document #: 38-05556 rev. *a page 30 of 30 document history page document title: cy7c1371d/cy7c1373d 18-mbit (512k x 36/1 mbit x 18) flow-through sram with nobl? architecture document number: 38-05556 rev. ecn no. issue date orig. of change description of change ** 254513 see ecn rkf new data sheet *a 288531 see ecn syt edited description under ?ieee 1149.1 serial boundary scan (jtag)? for non-compliance with 1149.1 removed 117 mhz speed bin added lead-free information for 100-pin tqfp , 119 bga and 165 fbga packages added comment of ?lead-free bg packages availability? below the ordering infor- mation

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